1. Field of the invention
The present invention relates to a semiconductor device, and more specifically a semiconductor device having therein a voltage step-up control circuit.
2. Description of related art
Recently, an operating voltage range of semiconductor memories is ordinarily of 5.0 V.+-.10%, but an operating voltage range of low voltage driven semiconductor memories is ordinarily 3.0 V.+-.10% or 3.3 V.+-.10%. In addition, the low voltage driven semiconductor memories are provided with a voltage step-up control circuit for stepping up a voltage to be applied to word lines of the memory, to a voltage higher than a power supply voltage supplied from an external.
However, this conventional voltage step-up control circuit is so configured to step up a word line voltage whatever power supply voltage is supplied, and therefore, there often occurs a problem of unreliability such as breakdown of a gate oxide film of a semiconductor MOS transistor used in the memory.
In order to avoid this problem, for example, Japanese Patent Application Laid-open Publication No. Showa 62-177787 proposed a voltage step-up control circuit so configured to detect a change of a power supply voltage, and to change a voltage step-up amount for the word line voltage in such a manner when the power supply voltage is high, the voltage step-up amount is made small so as to prevent an excessive large voltage from being applied to the word line.
Now, this proposed voltage step-up control circuit will be described with the drawings:
Referring to FIG. 1, the proposed voltage step-up control circuit includes a power supply voltage detecting circuit 61 outputting a power supply voltage detection signal .phi.4, a word line voltage step-up circuit 62 receiving the power supply voltage detection signal .phi.4 and a voltage voltage step-up start signal .phi.3 and outputting an output voltage V2, and a word line selecting circuit 63 receiving the output voltage V2. The power supply voltage detecting circuit 61 is configured to detect a voltage of a power supply and to output the power supply voltage detection signal .phi.4 for controlling a charging time of a voltage step-up capacitor (not shown in FIG. 1) internally provided in the word line voltage step-up circuit 62, in such a manner that when the power supply voltage is high, the charging time is shortened, and when the power supply voltage is not higher than an ordinary level, the charging time is elongated, with the result that a range of a usable operating voltage is increased.
Next, the proposed voltage step-up control circuit will be described in detail.
Referring to FIG. 2, the power supply voltage detecting circuit 61 includes P-channel transistors 29 and 32 and N-channel transistors 30, 31 and 33, which are connected as shown. The transistors 29, 30 and 31 are connected in series between the power supply voltage VCC and ground in the named order so as to generate, at a connection node between the transistors 29 and 30, a reference voltage VREF which constitutes a reference for the power supply voltage. This reference voltage VREF depends upon a threshold of the transistors 30 and 31, but is independent of the power supply voltage VCC.
The transistors 32 and 33 are connected in series between the power supply voltage VCC and the ground in the named order in the form of a CMOS inverter. Gates of the transistors 32 and 33 are connected in common to receive the reference voltage VREF, so that the transistors 32 and 33 are controlled by the reference voltage VREF generated by the transistors 29, 30 and 31. Drains of the transistors 32 and 33 are connected in common to generate the power supply voltage detection signal .phi.4 indicative of the result of the comparison between the reference voltage VREF and the power supply voltage VCC. Thus, when the power supply voltage VCC is higher than the reference voltage VREF, the power supply voltage detection signal .phi.4 is brought to a high level, and when the power supply voltage VCC is not higher than the reference voltage VREF, the power supply voltage detection signal .phi.4 is brought to a low level.
Referring to FIG. 3, the word line voltage step-up circuit 62 includes buffers 34 and 36, a voltage step-up capacitor 35, a NOR circuit 42 and a delay selection circuit 43 having a pair of delay circuits 40 and 41, which are connected as shown. Specifically, the buffer 34 has an input receiving the voltage step-up start signal .phi.3 and an output connected to one end of the voltage step-up capacitor 35 so as to charge the voltage step-up capacitor 35 from the one end of the capacitor 35. The output of the buffer 34 is also connected to an output of the word line voltage step-up circuit 62 for outputting the output voltage V2.
The delay selection circuit 43 includes a NAND circuit 38 having one input connected to receive the voltage step-up start signal .phi.3 and another input connected to receive through an inverter 37 the power supply voltage detection signal .phi.4, the delay circuit 40 having an input connected to an output of the NAND circuit 38 and an output connected one input of the NOR circuit 42, another NAND circuit 39 having one input connected to receive the voltage step-up start signal .phi.3 and another input connected to directly receive the power supply voltage detection signal .phi.4, and the delay circuit 41 having an input connected to an output of the NAND circuit 39 and an output connected the other input of the NOR circuit 42. Thus, the NOR circuit 42 outputs a delayed signal .phi.5 of the voltage step-up start signal .phi.3, and this delayed signal .phi.5 is applied to an input of the buffer 36, which in turn has an output connected to the other end of the voltage step-up capacitor 35 so as to charge the voltage step-up capacitor 35 from the other end of the capacitor 35.
Now, operation of this voltage step-up circuit 62 will be described. When the voltage step-up starting signal .phi.3 is activated, the buffer 34 is driven to start the charging of the voltage step-up capacitor 35. Here, when the power supply voltage VCC is higher than the ordinary supply voltage, since the power supply voltage detection signal .phi.4 is at the high level as mentioned above, the delay selection circuit 43 selects the delay circuit 40, so that the delayed signal .phi.5 of the voltage step-up starting signal .phi.3 outputted from the delay circuit 40 is applied through the NOR circuit 42 to the buffer 36. When the delayed signal .phi.5 changes from the high level to the low level, the voltage step-up operation is started.
On the other hand, when the power supply voltage VCC is not higher than the ordinary supply voltage, since the power supply voltage detection signal .phi.4 is at the low level as mentioned above, the delay selection circuit 43 selects the delay circuit 41 which has a delay time longer than that of the delay circuit 40, so that the delayed signal .phi.5 of the voltage step-up starting signal .phi.3 outputted from the delay circuit 41 is applied through the NOR circuit 42 to the buffer 36. When this delayed signal .phi.5 changes from the high level to the low level, the voltage step-up operation is started, similarly to the case that the power supply voltage VCC is higher than the ordinary supply voltage.
As seen from the above, when the power supply voltage VCC is low, the delay circuit 41 having a long delay time is selected, so that a sufficient charging time is ensured for the voltage step-up capacitor 35. Thus, the potential of the word line can be sufficiently elevated. On the other hand, when the power supply voltage VCC is high, the delay circuit 40 having a short delay time is selected, so that the charging time for the voltage step-up capacitor 35 is limited. Namely, the charging amount of the word line is limited so that the potential of the word line is elevated by only a small degree, and namely, the potential of the word line is restricted to a relatively low level.
As seen from the above, the conventional voltage step-up control circuit as mentioned above is configured to change the charging time of the voltage step-up capacitor, dependently upon whether or not the power supply voltage is higher than the ordinary supply voltage. In other words, even when the power supply voltage is sufficiently high, the potential step-up is carried out. Thus, if an excessive high voltage is applied to the word line, the gate oxide film of the semiconductor MOS transistor used in the memory is often broken.